This application claims the benefit of Japanese Application No. JP 2001-175579, filed Jun. 11, 2001 in the Japanese Patent Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device used as a high voltage driver to drive and control a power supply or other equipment.
2. Description of the Related Art
An integrated circuit used as a high voltage driver to drive and control a power supply generally includes a structure to isolate a high voltage portion from a low voltage portion.
Commonly used types of isolating structures include junction a isolation structure using a pn junction and a dielectric isolation structure using a dielectric, such as SiO2. In the junction isolation, a p-type substrate, for example a wafer, may be used having a low concentration n-type epitaxial layer formed on a surface of the wafer. A deep p-type diffusion region is formed in the epitaxial layer to form an n-type island that is three dimensionally divided by a pn junction. A driver circuit including a CMOS for example, is fabricated in the n-type island. A high breakdown voltage is achieved by applying reverse voltage between the n-type island and the p-type substrate to electrically isolate the n-type island using a junction capacitance.
In the dielectric isolation, silicon n-regions are formed that are electrically isolated each other by SiO2 selectively formed in a silicon substrate. An electric circuit is formed in each silicon n-region, where the electric circuit operating at a different base potential from a base potential of the other silicon n-regions. Thus, a high breakdown voltage is achieved in the dielectric isolation.
Japanese Unexamined Patent Application Publication No. H9-55498 discloses a method for junction isolation, in which only a planar junction performs isolation using a conventional silicon wafer, without using an epitaxial wafer that is commonly used in junction isolation. This isolation structure can be regarded as a kind of self-isolation structure. Japanese Unexamined Patent Application Publication No. 2000-58673 discloses a structure combining junction isolation and trench isolation and a trench isolation structure that forms an insulating layer along the surface of a trench.
The junction isolation structure needs relaxation of an electric field concentration at the pn junction appearing on the substrate surface. A commonly used method for the relaxation is a RESURF (reduced surface electric field) structure.
When a reverse bias potential is applied between an isolated n-type region and a p-type substrate, a parallel plane junction corresponding to a bottom of the planar junction develops a depletion layer parallel to the substrate surface. However, an end portion of the n-type region hardly extends the depletion layer and tends to generate the electric field concentration. The RESURF structure sets the impurity concentration in the end portion of the n-type region to a low value so as to facilitate expanding the depletion layer in this portion.
Another structure called double RESURF structure is also used for the terminating structure. A feature of the double RESURF structure is addition of a low concentration pxe2x88x92 region on the surface of the end portion of the n-type region compared to the single RESURF structure. When a reverse potential is applied between a isolated n-type region and a p-substrate of the double RESURF structure, depletion layers expand from both the pxe2x88x92 region on the surface region and the p-substrate in the end portion of the n-type region.
The following describes an example of a specific construction and operation of an integrated circuit having the double RESURF structure. FIG. 9 is a plane view of an example of a construction of a conventional high voltage driver integrated circuit.
The high voltage driver of FIG. 9 has the double RESURF structure. A high voltage IC chip 90 includes three regions 901 forming floating-potential-based circuits for a U-phase, a V-phase, and a W-phase of an upper arm and a region 902 forming a ground-potential-based circuit.
Each of the regions 901 forming the floating-potential-based circuits is surrounded by a high voltage junction terminating structure 903. FIG. 10 is a cross-sectional view showing a structure along a line B-Bxe2x80x2 in the conventional integrated circuit of FIG. 9.
FIG. 11 is a cross-sectional view showing a structure along a line C-Cxe2x80x2 in the conventional integrated circuit of FIG. 9. The conventional integrated circuit illustrated in FIGS. 10 and 11 includes a region 901 forming a floating-potential-based circuit formed in an n-region 92 U-phase in the surface region of a p-substrate 910 and a pxe2x88x92 region 902 forming a ground-potential-based circuit formed in an n-region 702. The pxe2x88x92 region 902 is formed in a surface region of a p+ region 801.
Each of the n-region 92 and the n-region 702 contains various semiconductor devices composing a control circuit. As examples of such semiconductor devices, FIGS. 10 and 11 show a P-MOS (P channel MOS transistor) and an N-MOS (N channel MOS transistor) in each of the n-regions.
A symbol Vcc in the n-region 702 indicates a wiring of a power supply of the lower arm (not shown). An electric potential of the wiring Vcc with respect to the ground potential GND is usually in a range from 10 to 20 volts, for example.
A high voltage junction terminating structure 903 is formed around the n-region 92 and the n-region 98 that is adjacent to the n-region 92. The n-region 98 is occasionally formed simultaneously in a process forming the n-region 92.
A symbol VUL in the n-region 92 indicates a base potential of the floating-potential-based circuit, and a symbol VUH indicates a power supply potential of the floating-potential-based circuit. The voltage of an upper arm power supply is given by VUHxe2x88x92VUL that is a potential difference between the potential VUH and the potential VUL. The voltage VUHxe2x88x92VUL is set to a value between 10 and 20 volts, for example.
A wiring at the base potential VUL connects to a midpoint of two IGBTs in upper and lower arms that are driven by the high voltage driver circuit. More specifically, the midpoint is the point at which an emitter of an upper arm IGBT and a collector of a lower arm IGBT join together. The base potential VUL changes rapidly in the switching process of the IGBT between 0 and 600 V for an IC of a withstand voltage of 600 V-class, or between 0 and 1,200 V for an IC of a withstand voltage of 1,200 V-class. A variation rate dV/dt of the potential VUL rises up to 10 to 20 kV/ps in some cases.
FIG. 9 shows a three phase driver IC, which has two other n-type regions for a V-phase and a W-phase having the floating-potential-based circuits on the p-substrate 910 as well as the n-region 92 for the U-phase. The base potentials VVL and VWL in these n-type regions for V- and W-phases also change rapidly in the switching process of the IGBTs like the potential VUL in the n-region 92 for the U-phase. Junction capacitance exists at each pn junction formed in the above-described conventional integrated circuit, which implies existence of a type of capacitor.
When a voltage with a rapidly changing waveform dV/dt is applied to this capacitor, a charging current or a displacement current Cxc3x97dV/dt flows at a whole surface of the pn junction, where C is a capacitance of the capacitor. This charging current drives the parasitic transistors 911 and 912 shown in FIGS. 10 and 11, as described below. This may cause malfunction of the circuit and device destruction, which has been a problem with the conventional integrated circuit.
FIG. 12 is a cross-sectional view along the line B-Bxe2x80x2 of FIG. 9 showing the conventional integrated circuit, to which an example of a latch-up current is added. FIG. 13 is a cross-sectional view along the line C-Cxe2x80x2 of FIG. 9 showing the conventional integrated circuit, to which an example of the latch-up current is added.
In the conventional self-isolation structure, latch-up current indicated by a thick line in FIGS. 12 and 13 may flow along a parasitic thyristor consisting of the p-region 93, the n-region 92, the p-substrate 910, and the n-region 702. FIG. 14 is a cross-sectional view at a portion corresponding to the line B-Bxe2x80x2 of FIG. 9 of the conventional integrated circuit, in which a means to avoid the latch-up current is provided.
In the conventional integrated circuit shown in FIG. 14, a deep guard-ring is formed surrounding the diffusion regions constituting an elementary device by means of an ion implantation followed by thermal diffusion. Because making the deep guard-ring involves lateral extension of the diffusion area of the guard-ring, a distance between the diffusion n-regions in adjacent elementary devices need to be enlarged.
This situation causes a large chip size. Therefore, this conventional isolation means is unfavorable. The conventional dielectric isolation structure does not cause the above-described parasitic action because the parasitic thyristor and a parasitic transistor do not exist in the structure. However, the structure suffers from high costs due to wafer processing.
Junction isolation structure allows adjusting impurity concentration and a depth of the isolation region more easily than a self-isolation structure by using the epitaxial wafer. Accordingly, a construction can be produced that avoids parasitic action. However, the manufacturing cost for the epitaxial wafer is higher than that for a non-epitaxial wafer in the self-isolation structure.
The combined structure of the junction isolation and the trench isolation that is disclosed in Japanese Unexamined Patent Application Publication No. 2000-58673 can not be applied to a high voltage IC that needs isolation between a high potential portion and a low potential portion in one chip at a potential difference of 600 to 1,200 volt classes.
In the known trench isolation structure, only such a type has been provided, in which a dielectric layer is formed along a trench wall. However, a type of trench isolation structure that is employed in a semiconductor device according to the present invention has never been disclosed, in which a conductive film on the trench wall or a polysilicon is buried in trench contacts with a p-substrate near the trench.
The present invention has been made in view of the above-described problems in the conventional integrated circuits, and according to the invention a semiconductor device is provided applicable to a high voltage driver that hardly suffers from malfunction or device destruction.
At first, an integrated circuit structure using the combination of the self-isolation structure and the trench isolation structure will be described. Specifically, a deep trench is formed in a surface region of a p-substrate surrounding diffusion regions that may become at a different electric potential from other regions. Examples for such diffusion regions are high voltage junction terminating structure and a region for forming a ground-potential-based circuit.
At first, an integrated circuit structure using the combination of the self-isolation structure and the trench isolation structure will be described. Specifically, a deep trench is formed in a surface region of a p-substrate surrounding diffusion regions that may become at a different electric potential from other regions. Examples for such diffusion regions are high voltage junction terminating structure and a region for forming a ground-potential-based circuit.
Then, one of the following three procedures is executed on the trench. (1) A high concentration p+ type region is formed on an inner wall of the trench formed in the surface region of the p-substrate. A conductive film, which is an electrode made of metal, for example, is formed on the surface of the p+ type region. The conductive film is grounded so that an electric potential of the conductive film equals the potential of the p-substrate near the trench, the latter potential being at a ground (GND) level. As a result, the potential of the conductive film, that is, a potential of the high concentration p+ type diffusion layer is held at the ground potential level, which is lower than, for example, the potential of Vcc in a region forming a ground-potential-based circuit.
(2)The trench is filled with a high concentration of p+ type silicon. This p+ type silicon is then heat-treated to reduce an electrical resistance and to ensure an electrical connection of the p+ type silicon to the p-substrate. An electrode is attached onto a top surface of the p+ type silicon and grounded so that a potential of this electrode equals a potential of the p-substrate near the trench, which is at the electrical potential level of the ground. As a result, the potential of the high concentration p+ type silicon is held lower than, for example, the potential of the n-type region 202 that forms the region forming a ground-potential-based circuit.
(3)The trench is filled with a dielectric. This structure can be regarded as a fusion of a self-isolation structure and a dielectric isolation structure. As a result, this structure is advantageous in manufacturing costs compared with manufacturing an entire structure by the dielectric isolation.
Next, the integrated circuit structure combining junction isolation structure and trench isolation will be described. This structure accomplishes isolation between regions by forming a trench in an epitaxial layer. Then, one of the above-described three procedures is executed on the trench.
These together with other objects and advantages, which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part thereof, wherein like numerals refer to like parts throughout.